System and method for forming high resolution electronic circuits on a substrate

ABSTRACT

A system and method for forming high resolution electronic circuits on a substrate is provided. The system ( 10 ) includes a substrate ( 12 ), a source of radiant energy ( 34 ) and a focusing means ( 16 ). The source of radiant energy ( 34 ) directs an energy beam ( 14 ) through the focusing means ( 16 ) in order to direct a focused energy beam ( 18 ) onto the surface of the substrate ( 12 ). The focused energy beam ( 18 ) creates a plurality of channels ( 20 ) in the surface of the substrate ( 12 ). A paste applicator ( 22 ) fills the channels ( 20 ) with an electrically conductive paste ( 24 ). Once heated and cured, the electrically conductive paste ( 24 ) makes up the electrically conductive pathways of the electronic circuit.

RELATED APPLICATIONS

This patent application is a Divisional patent application of co-pendingapplication Ser. No. 11/325,519, filed on 5 Jan. 2006 which was aContinuation-In-Part of patent application Ser. No. 10/612,904 filed on7 Jul. 2003, now U.S. Pat. No. 7,014,727.

The entire disclosure of the prior application Ser. No. 11/325,519 forwhich a Declaration is supplied, is considered a part of theaccompanying Divisional Application, and is hereby incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The subject invention relates to a system and method for forming highresolution electronic circuits on a substrate. In particular, thepresent invention directs itself to a processing system utilizing asource of radiant energy for the formation of a series of channels in asubstrate. More particularly, the invention directs itself to a computercontrolled system allowing a user to create a predefined series ofchannels in a substrate, the series having a user-selectable set ofdepths and dimensions.

Additionally, the present invention directs itself to a processingmethod including the steps of: forming at least one channel in asubstrate with a focused energy beam, cleaning the substrate to removeresidue from the channel-forming step, filling the channels with anelectrically conductive paste, and heating the substrate in order tocure the electrically conductive paste. More particularly, the inventiondirects itself to a method of fabricating electronic circuits on asubstrate where the channel-forming step allows for the creation ofpatterns for the electronic circuitry of variable size, shape, and depthon or in the substrate.

2. Prior Art

Methods for forming electronic circuitry on substrates are well-known inthe art. In general, such prior art methods include a building processwherein thin layers of dielectric and electrically conductive materialare sequentially formed on a base substrate using conventionalsemiconductor processing techniques. Dielectric layers are typicallyformed by the sequential steps of spin-coating the dielectric material,curing, pattern-etching with a plasma etch process to form viaapertures, and filling the apertures through electroplating orsputtering. The metal layers are typically formed by sequential steps ofsputtering a thin chromium layer (for adhesion to the dielectric layer),sputtering an initial copper layer over the chromium layer, defining theelectrical traces by either additive or subtractive methods, andremoving the excess copper and chromium between the electrical traces.

Typical additive methods use a thin initial copper layer (seed layer),then form a photo resist layer over the thin copper layer and pattern itto remove photo resist where the signal traces are to be located, andthereafter plate a much thicker copper layer into the photo resistpattern. Typical subtractive methods use a thick initial copper layer,then form a photo resist layer over the thick copper layer and patternit in order to remove photo resist in areas where there are signaltraces. Thereafter, exposed copper is etched away. The aforementionedbuilding process involves numerous steps and is a relatively expensiveprocedure. A defect in the formation of one layer may ruin the entiresubstrate. Current trends in the industry are biased toward increasingthe density of signal lines and vias. This, in turn, increases cost ofthe building process and further increases the chance of a defectoccurring.

Planar conductor patterns on plastic or other substrate materials areoften used for interconnection of electronic components. In particular,plastic flex circuits have found broad application in theinterconnection of semiconductor chips and small passive electroniccomponents in miniature electronic devices. Similar approaches are usedin the packaging of semiconductor integrated circuits to redistributeelectronic connections to comply with the requirements of particularapplications. The applications also include medical devices forimplantable sensors and associated drug delivery telemetry to sensorsfor Unmanned Aerial Vehicles (UAVs).

Plastic substrate materials offer the desirable characteristics ofmechanical flexibility, low cost, and lightweight. However, nearly allplastic materials exhibit irreversible damage when subjected toprocessing temperatures above 400° C. As a consequence, conductorpatterns on plastic substrates are normally produced byphotolithographic patterning and etching of a metal film deposited atlow temperatures over the entire substrate surface or by stencilprinting of polymer-based conductive inks. Both of these approaches havesignificant drawbacks. Etching is a subtractive process that requiresmore than eight process steps, poorly utilizes conductor materials, andgenerates a waste stream of process chemicals. Stencil printing ofpolymers or other materials is limited in the spatial resolution ofprinted features and the corresponding density of conductive lines.

Pastes that can be applied to ceramic substrates by stenciling processesand that cure at temperatures in the range of 800° C. are well-known inthe prior art. Due to their high curing temperatures, they are notapplicable to polymer substrates. Recent advances in materialstechnology, however, now allow for production of metallic powders withwell-controlled particulate dimensions in the micron range. Metallicprecursor compounds that cure at low temperatures by decomposing to formmetal species and volatile gases also have been identified. When mixedwith appropriate solvents, surfactants, and adhesion promoters, thesematerials can be used to manufacture pastes that cure at temperatures ofless than 250° C. to form high-quality electrical conductors.

It is a purpose of the subject invention to provide a method forcreating electrical circuitry on a substrate which reduces manufacturingcosts and defects and, thusly, enables board manufacturers to keep upwith the demands of the semiconductor and circuitry industries.

Filling laser-drilled via holes with conductive pastes that can be curedat low temperatures provides an approach to electrical connection of thetop and bottom surfaces of a substrate or between conductor arrays ondifferent levels of a multi-substrate laminated stack. Since the samelaser tool and filling process can be used for production of bothchannels and through holes, planar conductor arrays on the surface ofthe substrate and conductive vias through it can be fabricated in asingle sequence of operations.

One such prior art method of forming electrical circuitry on a substrateis shown in U.S. Pat. No. 4,417,393. This reference is directed to amethod of fabricating high density electronic circuits having verynarrow conductors. Although this reference describes the use of standardthick film materials, the reference does not address the issue ofthermal compatibility of the filler material and the substrate. Theprior art includes several attempts to address the challenge ofconductor or via fabrication on low-temperature substrates.Additionally, this reference describes the use of a laser to mill finelines and holes in the substrate which are then filled with conductivematerials to produce planar conductor arrays and vias. Although thereference describes the use of standard thick film materials, it doesnot address the issue of thermal compatibility of the filler materialand the substrate.

U.S. Pat. No. 4,763,403 is directed to a method of making an electroniccomponent. This reference teaches the use of conductive epoxy paste forthe interconnection of conductor patterns.

U.S. Pat. No. 6,163,957 describes a similar technique for production ofvias using laser-drilled holes in a substrate covered by an auxiliaryfilm. In both of these references, the conductor pattern is formedthrough a photo-lithographic process. The reference directs itself tothe creation of channels through direct application of radiant energy.

Another such prior art method of forming electrical circuitry on asubstrate is shown in U.S. Pat. No. 5,666,722. This reference isdirected to a method of manufacturing printed circuit boards. Thissystem teaches the fabrication of planar conductor arrays through vaporor plasma deposition of metals onto a substrate containing laser cutchannels followed by the abrasion of the substrate surface. Thisapproach provides high spatial resolution and eliminates the use ofphoto-lithographic etching, but is wasteful of applied metallic materialand may require additional processing steps to achieve desired conductorthickness.

U.S. Pat. No. 5,091,339 is directed to trenching techniques for formingvias and channels in multilayer electrical interconnects. This systemteaches the use of channel and hole patterns formed by plasma or laseretching through multiple masks with subsequent filling by conductivematerials. The system does not utilize the formation of channels formedthrough direct application of radiant energy to the substrate surface.

U.S. Pat. No. 4,912,844 describes the use of a punch to produce cavitiesand grooves in a suitable deformable substrate. This reference teachesthe use of a punch tool in order to press cavities and grooves intodeformable electrically insulating substrates laminated by metallic foilto produce cavities and grooves in the laminated surface. Removal ofmaterial on the unindented portion of the laminated substrate surface bymechanical or etching techniques then results in formation of aconductor array pattern. This approach is wasteful of conductivematerial and may be applied only to selected substrate materials.

Additionally, U.S. Pat. No. 4,336,320 teaches the filling ofphotolithographically defined channels with thick film conductor pasteand U.S. Pat. No. 4,508,753 teaches the filling of a pattern engraved inan applied insulating coating with conductive paste to fabricateconductor patterns on high-temperature substrates.

The prior art includes several attempts to address the challenge ofconductor or via fabrication on low-temperature substrates. U.S. Pat.No. 4,763,403 describes the use of conductive epoxy paste forinterconnection of conductor patterns. U.S. Pat. No. 6,263,957 describesa similar technique for production of vias using laser-drilled holes ina substrate covered by an auxiliary film. In both of these references,the conductor pattern is formed through photolithographic processes.Additionally, U.S. Pat. No. 5,666,722 teaches the fabrication of planarconductor arrays by vapor or plasma deposition of metals onto asubstrate containing laser cut channels followed by abrasion of thesubstrate surface. This approach provides high spatial resolution andeliminates the use of photolithographic etching, but it is wasteful ofapplied metallic material and may require additional process steps toachieve desired conductor thickness.

U.S. Pat. No. 5,091,339 describes the use of channel and hole patternsformed by plasma or laser etching through multiple masks with subsequentfilling by conductive material. U.S. Pat. No. 4,912,844 describes use ofa punch to produce cavities and grooves in a suitable deformablesubstrate and the provision of conductive material in the grooves toproduce conductor arrays. This reference teaches the use of a punch toolto press cavities and grooves into deformable electrically insulatingsubstrates laminated by metallic foil to produce cavities and grooves inthe laminated surface. Further, the reference provides for the removalof material on the unindented portion of the laminated substrate surfaceby mechanical or etching techniques, resulting in the formation of aconductor array pattern. This approach is wasteful of conductivematerial, may be applied only to selected substrate materials, andrequires fabrication of punching or embossing tools which are costly andsubject to wear.

In the prior art, laser processing has been used to produce small viaholes in plastic electronic substrates, as shown in U.S. Pat. No.4,959,119. Electroplating of the inner surfaces of these holes is alow-temperature technique commonly used to provide an electricallyconducting path or via between the two sides of the substrate. U.S. Pat.No. 5,422,190 has described use of thick film conductive pastes to fillvia holes in electronic substrates that can be fired at temperaturesexceeding 700° C., which are needed to cure these thick film pastes.However, substrates that are damaged by exposure to these temperaturescannot be used in combination with the thick film pastes, such as thosedescribed in U.S. Pat. No. 5,422,190.

None of the prior art provides for a combination of steps as hereinpresented comprising a method for forming electronic circuits on asubstrate which allows for a maximum of efficiency and costeffectiveness with a minimum of defects. None of the prior art methodsinclude the combined steps of laser milling an uncoated surface of asubstrate to form a series of channels having user-defined depths anddimensions.

SUMMARY OF THE INVENTION

The present invention provides for a system and method for creating highresolution electronic circuits on a substrate. The method includes thesteps of forming at least one channel in a substrate with a focusedenergy beam, cleaning the substrate to remove residue from the formationstep, filling the channels with an electrically conductive paste, andheating the substrate in order to cure the electrically conductivepaste. The system for implementing the method for creating highresolution electronic circuits on a substrate includes a source ofradiant energy and a focusing means for directing a focused energy beamonto the surface of a substrate. The substrate is mounted on atranslatable table, which allows for the formation of channels havinguser-defined depths and thicknesses.

It is a principle objective of the subject system and method of forminghigh resolution electronic circuits on a substrate to provide anefficient process for creating electrical circuitry on a substratematerial.

It is a further objective of the subject system and method for forminghigh resolution electronic circuits on a substrate to provide a systemand method where channels are formed in the substrate material havinguser-defined depths and thicknesses.

It is a further objective of the subject invention to provide a systemand method of forming high resolution electronic circuits on a substratewhere the electrically conductive material is heated in order to shapethe material, increase the material's strength and remove impuritiesfrom the electrically conductive material.

It is an important objective of the present invention to provide asystem and method for forming high resolution electronic circuits on asubstrate which include user-defined and user-selectable depths anddimensions of the channels formed in the substrate by the focused energybeam.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of the system for forming highresolution electronic circuits on a substrate;

FIG. 2 is a cross-sectional view of the system for forming highresolution electronic circuits on a substrate in operation;

FIG. 3 is a cross-sectional view of the substrate subsequent to the stepof channel formation;

FIG. 4 is a cross-sectional view of the milled substrate during the stepof conductive paste application;

FIG. 5 is a perspective view of the focusing means; and,

FIG. 6 is a perspective schematic view of a high resolution circuitformed on the substrate layer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIGS. 1 and 2, there is shown a system 10 forimplementing a method for forming high resolution electronic circuits ona substrate. The system 10 includes a source of radiant energy 34, afocusing means 16, and a substrate 12. The laser milling and drillingsystem 10 allows for the fabrication of planar conductor arrays havinghigh spatial resolution, compatibility with polymer and otherlow-temperature substrate materials and allows for the simultaneousfabrication of conductors and vias. Additionally, the process allows forthe efficient utilization of conductor materials, minimizes wastematerials created in the production process, and allows for a simple,rapid and inexpensive method for making changes in the conductor arraypatterns.

The source of radiant energy 34 may be a laser, a source of noncoherentlight, an electron beam generator, or any other suitable means forgenerating radiant energy. In the preferred embodiment of the invention,the source of radiant energy 34 is a diode-pumped, solid-state neodymiumlaser, such as a neodymium vanadate laser. In order to effectivelyablate the surface of substrate 12, it is preferred that the output ofthe laser 34 be frequency-tripled or frequency-quadrupled in order toproduce wavelengths shorter than 360 nm.

The source of radiant energy 34 is utilized for the production ofoptical, or other focused energy for the ablation of channels or viapatterns in substrate 12.

Substrate 12 may be a glass, a polyimide film, or any other suitablesubstrate composition. One such substrate composition which may be usedfor substrate layer 12 is a polyimide film known as KAPTON®, which isproduced by DuPont High Performance Materials of Circleville, Ohio.KAPTON® polyimide films are dielectric films which retain their physicalproperties over a wide temperature range. They have been used in fieldapplications where the environmental temperatures were as low as −269°C. and as high as 400° C. Polyimide materials are preferred forsubstrate 12 because polyimides exhibit high optical absorption in thewavelength range of frequency-converted laser emissions. Additionally,the substrate 12 may be formed from a dielectric material such asMICROLAM®, manufactured by W.L. Gore & Associates of Newark, Del.Further, the polymer materials-used to form the substrate 12 may also bein the form of liquid crystal polymer.

The source of radiant energy 34 generates an unfocused energy beam 14which, as shown in FIGS. 1 and 2, is directed to focusing means 16.Focusing means 16 may include optical lenses, rotatable and translatablemirrors, drive systems, a magnetic focusing system, or any othernecessary means for focusing unfocused energy beam 14 onto substrate 12.

In order to achieve high processing speeds, the source of radiant energy34 should be capable of producing several watts of average power atpulse repetition rates greater than 50 kHz. Focusing means 16 isemployed for rapid and precision controlled movement of the point atwhich the focused or imaged laser beam 18 impinges on the surface ofsubstrate 12. The radiation generated by the radiant energy source 34 isnormally operated in a q-switched pulse mode. FIG. 5 illustrates severaloptical components which may be utilized in focusing means 16. As shown,unfocused energy beam 14 impinges upon first mirror 28. First mirror 28is driven by galvanometer scanner 30. FIG. 5 represents only one exampleof components which may be used as a focusing means 16, and any othersuitable drive system may be utilized in order to rotate and/ortranslate mirror 28.

Unfocused energy beam 14 is reflected from mirror 28 to second mirror28′. Second mirror 28′ is, similarly, driven by a galvanometer scanner30′ in order to properly direct the beam. The unfocused energy beam isthen reflected from second mirror 28′ through optical lens 26. Lens 26is preferably an “F-theta” or telecentric objective lens. The opticallens 26 illustrated in FIG. 5 is suitable for the case when the sourceof radiant energy 34 is a laser or a source of non-coherent light.However, when radiant energy source 34 is an electron beam source, orother form of radiant energy, other suitable means for focusing theenergy beam may be utilized.

Once the energy beam passes through lens 26, the focused energy beam 18then impinges upon the surface of substrate 12. Mirrors 28 and 28′, andtheir respective drive means 30 and 30′ are utilized in order to scanthe focused energy beam 18 across the surface of substrate 12 along apre-selected path.

A computer control means (not shown) may be in electrical communicationwith the drive means 30 and 30′ in order to allow a user to selectivelyenter a beam path. The control means may be either set automatically,for creating a set of desired paths, or the system may be operatedmanually.

As shown in FIG. 2 of the Drawings, focused energy beam 18 createschannels 20 in substrate 12. In addition to the drive means 30 and 30′for the mirrors 28 and 28′, respectively, substrate 12 is mounted on atranslation stage 36. The translation stage 36 allows for translation ofsubstrate 12, with respect to the focusing means 16 and the focusedenergy beam 18, along two orthogonal axes, such as the X and Y Cartesianaxes.

The computer control means may also be in electrical communication withthe translation stage 36 in order to control the translation of thesubstrate 12. Control of translation stage 36 may either follow pre-setpatterns or be manually operated by the user.

Operation of laser 34 at power levels high enough to produce ablation orvaporization of the substrate material while the focused energy beam 18is rapidly scanned across the surface of substrate 12 provides a meansfor fabrication of patterns of channels and holes of controlled depth insubstrate 12. Each laser pulse 18 removes a layer of material of lessthan a few microns thickness from the illuminated region of thesubstrate 12. The depth and shape of ablated channel and hole structuresmay thereby be defined by controlling the number of pulses delivered toeach illuminated region as beam 18 is scanned over it.

It has been found that laser beams with a Gaussian or near-Gaussianintensity profile yield groove bottoms and sidewalls having optimalsmoothness. Consistent, smooth conductor surfaces are particularlydesirable for high-frequency (>400 MHz) applications.

The depth and shape of the ablated channel and hole structures isdefined by controlling the number of pulses, and the pulse rate,delivered to each illuminated region as the beam is scanned over it. Useof the scanned laser beam, rather than laser projection of a fixed maskpattern onto the substrate, allows the channel and hole patterns to beeasily changed by modification of the system control software. Withcomputer control, the pulsed output of the laser is synchronized withthe motion of the translation stages and galvanometer system to achieveuniform overlap of laser pulses and smooth surfaces of ablated features.

In an alternative embodiment, a circular aperture (not shown) may beadded to focusing means 16. It has been found that clipping the lowerintensity “wings” of the energy beam by means of a circular aperturesized to transmit roughly 80% of the beam's energy offers a goodcompromise between smooth machined surfaces and sharper line definition.

The path of the laser beam 18 may be determined and optimized using aCAD, or similar, program before downloading the sequence into thegalvanometer scanners 30 and 30′. Laser pulsing is carefullysynchronized with the beam motion in order to permit consistent depthcontrol. Unintended overlapping of pulses, dwell during acceleration anddeceleration of the beam, overshooting and undershooting of the beam,and other inaccuracies can result in unacceptable variation in channeldepth. The step of laser ablation is preferably accomplished using alaser operating at wavelengths shorter than 400 mm. Preferably, thelaser is a frequency-converted solid state laser.

FIG. 3 illustrates the substrate 12 following the application of focusedenergy beam 18. Channels 20 are now formed in substrate 12 following adesired pattern. When a material, such as MICROLAM®, is utilized in theformation of substrate 12, it is preferred that the energy source 34 bea frequency-tripled neodymium laser operating at a wavelength of 355 nm.

Following laser patterning, the substrate 12 is cleaned in order toremove any residue or debris left over from the ablation andvaporization of substrate material. The cleaning of the laser ablationdebris from substrate 12 may be performed by sonication in a liquid.Where cleaning is performed by sonication in a liquid, the cleaningprocess is followed by drying the substrate 12 in an oven to remove theremaining liquid.

The channels 20 are then filled with a low-temperature electricallyconductive paste material. One such suitable material is PARMOD® PRA-311silver paste, made by Parelec, Inc. of Rocky Hill, N.J. PARMOD® silverpastes and inks are disclosed in U.S. Pat. Nos. 5,882,722; 6,036,889;6,143,356; and, 6,379,745.

The material used to fill channels 20 may be an electrically conductivepaste or slurry material. The electrically conductive paste or slurrymaterial 24, in the preferred embodiment, is formed of metallicparticles and metallic precursor compounds. In the preferred embodiment,the metallic particles each have an average diameter of 5 micrometersand the metallic precursor compounds are chosen to include materialswhich convert to solid-phase electrically conductive materials attemperatures of less than 350° C. Further, the conductive fillermaterial may include liquid solvents. The liquid solvents may,preferably, include dipropylene glycol methyl ether added at a 1.1weight percentage. Additionally, the conductive filler material mayinclude compounds promoting adhesion of the solid phase conductivematerial, produced in the final heating stage of the substrate toconvert the conductive paste filler material to a solid phase conductivematerial, to the substrate 12. These adhesion-promoting compounds may bediamines.

The physical characteristics and chemical composition of conductivepastes used to fill the laser-produced channels and holes stronglyinfluence the degree to which the cured conductive material allows forlow curing temperatures, low conductor resistivity, line widths andfeature sizes on a small scale, strong adhesion between the conductivematerials and the polymer substrate, solderability, and the productionof smooth conductor surfaces for efficient high frequency performance.In order to determine a suitable conductive paste material, severalexperiments were performed utilizing different conductive materials.

Test patterns were fabricated for these experimental tests using a 355nm pulsed laser to produce arrays of channels having widths rangingbetween 15 microns and 1000 microns, formed in polyimide substrates.Channel patterns were filled with candidate conductive paste materials,cured at elevated temperatures, and evaluated for electricalconductivity, mechanical adhesion, and shrinkage. Because desiredfeature sizes are typically in the micron range, dimensions of theparticulates in the conductive pastes were limited to less than or equalto 5 micron average particle size. Results of the experiments performedwith various candidate materials are summarized in the examples below:

EXPERIMENT 1

The first material tested was a silver thick film formulated for use onceramic substrates. Channels in several test polymer substrates werefilled with the silver thick film using a doctor blade technique. Anumber of test substrates were baked in an oven at temperatures between200° C. and 300° C. for twenty minutes in order to explore the curingtemperature of the material. Electrical conductivity measurements weretaken of the test substrates. These tests demonstrated that the materialdid not become significantly conductive at temperatures below 300° C.

EXPERIMENT 2

The second material tested was composed of silver flake and silverneodecanoate in neodecanoic acid with a 6 to 1 ratio of silver flake tosilver neodecanoate. Channels in several test substrates were filledwith the second material using a doctor blade technique. After heatingthe substrate to 95° C. for one minute in a soft bake cycle, anymaterial remaining on the flat portion of the substrate surface wasremoved by abrasion. Test substrates were then baked at temperaturesbetween 150° C. and 300° C. for twenty minutes in order to explore thecuring temperature of the material. These tests demonstrated that thematerial became conductive at a cure temperature of approximately 200°C. and exhibited resistivity of approximately six times that of bulksilver. However, it was observed that the cured conductors exhibited alarge amount of shrinkage and poor adhesion to the polyimide substrate.

EXPERIMENT 3

The third material tested was similar to the second material, however,dipropylene glycol methyl ether was added at a 1.1 weight percent.Channels in several test substrates were filled with the material usinga doctor blade technique. After heating the substrate to 95° C. for oneminute in a soft bake cycle, any material remaining on the flat portionof the substrate surface was removed by abrasion. Test substrates werethen baked at temperatures between 150° C. and 300° C. for twentyminutes in order to explore the curing temperature of the material.These tests demonstrated that the material became conductive at a curetemperature of approximately 150° C. and exhibited resistivity ofapproximately six times that of bulk silver. Adhesion of the conductivematerial to the substrate was greatly improved with respect to thesecond material, and the conductor pattern adhered well to thesubstrate. Solderability of the material, using SnPb solder, was foundto be unacceptable for semi-conductor device applications.

EXPERIMENT 4

A fourth material, formed of Parmod® silver ink PRA-311, was utilized.This material is similar to the third material, but with the addition ofdiamine adhesion-promoting compounds. Channels in several testsubstrates were filled with the material using a doctor blade technique.After heating the substrate to 95° C. for one minute in a soft bakecycle, any material remaining on the flat portion of the substratesurface was removed by abrasion. Test substrates were then baked attemperatures between 150° C. and 300° C. for twenty minutes to explorethe curing temperature of the material. These tests demonstrated thatthe material became conductive at a cure temperature of approximately150° C. and exhibited resistivity of approximately six times that ofbulk silver. The conductor pattern adhered well to the substrate. Thesolderability of the material, using SnPb solder was found to beunacceptable, but acceptable solderability was demonstrated using SnPbAgsolder.

Technical and economic viability of the system is influenced by theemission characteristics of the laser used for channel ablation and themanner in which the laser emission is delivered to the substratesurface. Lasers operating at ultraviolet wavelengths are desirable,since ultraviolet beams can be focused to sizes compatible withfabrication of micron-scale features, and ultraviolet radiation isstrongly absorbed by many substrate materials. Operation of theultraviolet laser source in a pulsed mode with sub-microsecond pulseduration produces clean vaporization of substrate material illuminatedby the laser pulse with minimal damage to surrounding regions. The depthof substrate material removed by a single laser pulse is a function ofthe optical energy density in the illuminated region and typically is onthe order of 0.2-0.7 microns. Channels can be produced by overlappingsequential laser pulses on the substrate surface. The depth and surfaceroughness of such channels is largely a function of the optical energydensity at the substrate and the spatial offset of sequential pulses.

The volumetric rate of material removal is roughly proportional to theaverage optical power delivered to the substrate surface. This rateestablishes the throughput of the surface patterning operation. Sincehigh-power lasers typically generate optical power at lower cost,effective use of a high power laser source tends to increase throughputand reduce the cost of components produced by the system. Consequently,commercial viability of the system is influenced by the ability toutilize a high-power laser source. This requires that provisions be madefor very high pulse repetition rate operation of the laser and for veryhigh speed, extremely precise relative motion between the laser beam andthe substrate.

Using the fourth material (Experiment 4) and a computer-controlledhigh-speed laser ablation system comprising a 3 Watt, 355 nmfrequency-converted Nd:YAG laser, galvanometer-driven beam scanningmirrors, and high-speed stages equipped with a vacuum chuck for mountingplanar organic substrates, 3.7 cm×3.7 cm chip-scale packages werefabricated, which were characterized by a top layer containing 1038solder bump pads, 600 traces of 15-micron width, and total length of5564 mm, and 819 (40 micron) vias, and by a bottom layer containing 670(650 micron diameter) solder pads, and 160 traces of 15 micron width and464 mm total length.

After laser ablation of feature patterns, the substrate was cleaned bysonication in a mild detergent. The top side of the circuit was thenfilled with Parmod® PRA-311 using a doctor-blade technique and thecircuit was soft baked at 95° C. for one minute. After the first softbake, the doctor-blade technique was used to refill the ablated featureson the top side to compensate for shrinkage of the PRA-311 material, andthe substrate was again soft baked at 95° C. for one minute. Excessmaterial was then removed from the top surface of the substrate bylapping with a dry abrasive, and the substrate was baked at 150° fortwenty minutes.

After filling of the top side of the substrate, the bottom side wasfilled by a similar method. Adhesion of the conductor pattern to thesubstrate was tested by applying adhesive tape to the metalizedsubstrate and then pulling the tape away. Metal traces were found to beintact after this test. About 20% of the substrate area was covered withmetal, suggesting that alternative photolithographic techniques fordefining conducting traces and pads would have utilized approximatelyfive times as much metal for full coverage of the surface and etchedaway 80% of that in the process of trace and pad definition.

FIG. 4 illustrates paste applicator 22 applying electrically conductivepaste 24 to substrate 12 and filling channels 20 with the electricallyconductive paste 24. Following the application of the conductive paste24, substrate 12 and paste 24 is heated to a temperature greater than250° C. in order to cure the electrically conductive paste material 24.This results in a pattern of holes and channels 20 filled with theelectrically conductive paste. When PARMOD® is used as the electricallyconductive paste 24, once cured, the channels 20 are filled with asilver material having an electrical resistivity of approximately threeto six times that of bulk silver.

The channels or holes may be filled with a silver conductive pastematerial including silver flake and silver necadecanoate in neodecanoicacid with a 6 to 1 ratio of silver flake to silver neodecanoate.

The heating and curing of the electrically conductive paste 24 acts tonot only cure the material, but shape the conductive paste 24, increasethe material's strength and remove impurities from the electricallyconductive paste 24. The substrate 12 and electrically conductive pasteor slurry 24 are heated to a temperature of less than 250° C., in thepreferred embodiment, in order to convert the conductive paste or slurryfiller material 24 to solid-phase electrically conductive material. Inan alternative embodiment, the substrate may be baked at temperaturesless than 100° C. for a period of 1 to 30 minutes. The steps of fillingthe channels and soft baking of the substrate are sequentially repeateduntil the channels or holes are completely filled. Excess conductivefiller material is then removed from the upper surface of the substrateand the substrate is heated, once again, to temperatures of less than250° C. in order to convert the conductive paste filler material into asolid phase conductive material.

FIG. 6 illustrates a completed high resolution electronic circuit 32formed on a substrate material 12. The circuitry 32 illustrated in FIG.6 follows a user-defined path and set of parameters.

Although this invention has been described in connection with specificforms and embodiments thereof, it will be appreciated that variousmodifications other than those discussed above may be resorted towithout departing from the spirit or scope of the invention. Forexample, functionally equivalent elements may be substituted for thosespecifically shown and described, proportional quantities of theelements shown and described may be varied, and in the formation methodsteps described, particular steps may be reversed or interposed, allwithout departing from the spirit or scope of the invention as definedin the appended Claims.

1. A method for forming high resolution electronic circuits on asubstrate including the steps of: (a) forming at least one channel in asubstrate with a focused energy beam, (b) cleaning said substrate toremove residue from said step of forming at least one channel; (c)filling said at least one channel with an electrically conductive pasteor slurry material, said slurry material being formed of silverparticles and silver precursor compounds which convert to solid-phaseelectrically conductive materials at temperatures of less than 250° C.,said silver particles each having an average diameter of less than orequal to 5 micrometers; and (d) heating said substrate to temperaturesless than 250° C. to cure said electrically conductive paste or slurrymaterial.
 2. The method for forming high resolution electronic circuitson a substrate as recited in claim 1, wherein said substrate is formedof polyimide.
 3. The method for forming high resolution electroniccircuits on a substrate as recited in claim 1, wherein said focusedenergy beam is generated by a laser.
 4. The method for forming highresolution electronic circuits on a substrate as recited in claim 1,wherein said focused energy beam is directed by a movable mirror.
 5. Themethod for forming high resolution electronic circuits on a substrate asrecited in claim 4, wherein said movable mirror is user controlled. 6.The method for forming high resolution electronic circuits on asubstrate as recited in claim 1, wherein said focused energy beam isfocused by at least one optical lens.
 7. The method for forming highresolution electronic circuits on a substrate as recited in claim 1,wherein said step of forming at least one channel in a substrateincludes translation of said substrate along a pair of orthogonal axes.8. The method for forming high resolution electronic circuits on asubstrate as recited in claim 7, wherein said translation of saidsubstrate is user controlled.
 9. The method for forming high resolutionelectronic circuits on a substrate as recited in claim 1, wherein saidelectrically conductive paste or slurry material contains silver. 10.The method for forming high resolution electronic circuits on asubstrate as recited in claim 1, wherein said focused energy beam is afocused electron beam.
 11. A method for forming high resolutionelectronic circuits on a substrate including the steps of: (a) formingat least one channel in a substrate with a focused energy beam; (b)cleaning said substrate to remove residue from said step of forming atleast one channel; (c) filling said at least one channel with anelectrically conductive paste or slurry material, said electricallyconductive paste or slurry material including silver flake and silvernecadecanoate in neodecanoic acid with a 6 to 1 ratio of silver flake tosilver neodecanoate; and, (d) heating said substrate to temperaturesless than 250° C. to convert said electrically conductive paste orslurry material to a solid phase conductive material.
 12. The method forforming high resolution electronic circuits on a substrate as recited inclaim 11, wherein said step of cleaning said substrate includessonication in a liquid.
 13. The method for forming high resolutionelectronic circuits on a substrate as recited in claim 12, wherein saidsonication in said step of cleaning said substrate is followed by thestep of drying said substrate in an oven.
 14. The method for forminghigh resolution electronic circuits on a substrate as recited in claim11, wherein said electrically conductive paste or slurry materialfurther includes liquid solvents.
 15. The method for forming highresolution electronic circuits on a substrate as recited in claim 14,wherein said liquid solvents include dipropylene glycol methyl etheradded at a 1.1 weight percentage.
 16. The method for forming highresolution electronic circuits on a substrate as recited in claim 11,wherein said electrically conductive paste or slurry material furtherincludes compounds promoting adhesion of said solid phase conductivematerial to said substrate.
 17. The method for forming high resolutionelectronic circuits on a substrate as recited in claim 16, wherein saidadhesion-promoting compounds are diamines.
 18. The method for forminghigh resolution electronic circuits on a substrate as recited in claim11, wherein said substrate is formed of polymer materials.
 19. Themethod for forming high resolution electronic circuits on a substrate asrecited in claim 18, wherein said polymer materials include polyimidematerials.
 20. The method for forming high resolution electroniccircuits on a substrate as recited in claim 18, wherein said polymermaterials include liquid crystal polymers.
 21. The method for forminghigh resolution electronic circuits on a substrate as recited in claim11, wherein said step of forming at least one channel in said substrateis accomplished by using a laser operating at wavelengths shorter than400 nm.
 22. The method for forming high resolution electronic circuitson a substrate as recited in claim 21, wherein said laser is afrequency-converted solid state laser.
 23. The method for forming highresolution electronic circuits on a substrate as recited in claim 22,wherein said step of forming at least one channel in said substrateincludes the step of directing a laser beam generated by said laserusing galvanometrically-driven mirrors.
 24. A method for the fabricationof conducting elements on planar insulating substrates comprising thesteps of: (a) laser ablation of at least one channel or hole in asubstrate; (b) cleaning laser ablation debris formed in the step oflaser ablation from said substrate; (c) filling said channels or holeswith a silver conductive paste material, said silver conductive pastematerial including silver flake and silver necadecanoate in neodecanoicacid with a 6 to 1 ratio of silver flake to silver neodecanoate; (d)soft baking said substrate at temperatures of less than 100° C. for aperiod of 1 to 30 minutes; (e) sequentially repeating said steps offilling said channels or holes and said soft baking said substrate untilsaid channels or holes are completely filled; (f) removing excessconductive filler material from an upper surface of said substrate; and,(g) heating said substrate to temperatures of less than 250° C. toconvert said conductive paste filler material to solid phase conductivematerial.
 25. The method for the fabrication of conducting elements onplanar insulating substrates as recited in claim 24, wherein said stepof cleaning laser ablation debris includes sonication in a liquid. 26.The method for the fabrication of conducting elements on planarinsulating substrates as recited in claim 25, wherein said liquid iswater containing a mild detergent.
 27. The method for the fabrication ofconducting elements on planar insulating substrates as recited in claim25, wherein said sonication is followed by the step of drying saidsubstrate in an oven.
 28. The method for the fabrication of conductingelements on planar insulating substrates as recited in claim 24, whereinsaid step of removal of excess conductive filler material is performedby an abrasion process.
 29. The method for the fabrication of conductingelements on planar insulating substrates as recited in claim 24, whereinsaid conductive filler material includes liquid solvents.
 30. The methodfor the fabrication of conducting elements on planar insulatingsubstrates as recited in claim 29, wherein said liquid solvents includedipropylene glycol methyl ether added at a 1.1 weight percentage. 31.The method for the fabrication of conducting elements on planarinsulating substrates as recited in claim 24, wherein said conductivefiller material further includes compounds promoting adhesion of saidsolid phase conductive material to said substrate.
 32. The method forthe fabrication of conducting elements on planar insulating substratesas recited in claim 31, wherein said adhesion-promoting compounds arediamines.
 33. The method for the fabrication of conducting elements onplanar insulating substrates as recited in claim 24, wherein saidsubstrate is formed of a polymer material.
 34. The method for thefabrication of conducting elements on planar insulating substrates asrecited in claim 33, wherein said polymer material is a polyimidematerial.
 35. The method for the fabrication of conducting elements onplanar insulating substrates as recited in claim 33, wherein saidpolymer material includes liquid crystal polymer.
 36. The method for thefabrication of conducting elements on planar insulating substrates asrecited in claim 24, wherein said step of laser ablation is performedusing a laser operating at wavelengths shorter than 400 nm.
 37. Themethod for the fabrication of conducting elements on planar insulatingsubstrates as recited in claim 36, wherein said laser is afrequency-converted solid state laser.
 38. The method for thefabrication of conducting elements on planar insulating substrates asrecited in claim 36, wherein radiation generated by said laser isdirected to said substrate using galvanometrically-driven mirrors.